योगेश सिंह चौहान
Source: https://www.iitk.ac.in/hindi/yogesh-singh-chauhan Parent: https://www.iitk.ac.in/hindi/research
- मुख्य पृष्ठ
- संकाय
- योगेश सिंह चौहान
योगेश सिंह चौहान
PhD (Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland)
Professor, Departement of Electrical Engineering
शोध करना दिलचस्पी
Nanoelectronics Compact modeling of semiconductor devices (Bulk/SOI MOSFET, Multigate FET, Nanowire, UTBSOI and novel devices) SPICE Modelling of High Voltage/Power Semiconductor Devices (LDMOS, VDMOS, IGBT, HEMT etc.) BSIM model development and support (with BSIM Group at University of California Berkeley) Atommistic Simulation of Nanoscale Devices\ DC, CV and RF Characterization
https://home.iitk.ac.in/~chauhan/
Office
WL125\ Department of Electrical Engineering\ Indian Institute of Technology\ Kanpur, U.P. - 208016
Labs addresses: Nanolab (WL215)
- मूल जानकारी
- शोध करना दिलचस्पी
- संपर्क जानकारी
- Research Area
- विशेषज्ञता
- शिक्षा
- शिक्षण क्षेत्र
- व्यावसायिक जुड़ाव
- चयनित प्रकाशन
- पुरस्कार एवं फैलोशिप
- कीवर्ड
- पेशेवर अनुभव
Research Area
Research Areas for Specialization in Microelectronics, VLSI and Display Technologies
विशेषज्ञता
Compact Modeling
शिक्षा
PhD, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland ‐ 2004‐2007\ Thesis Title:Compact modeling of high voltage MOSFETs\ Thesis Supervisor:Adrian M. Ionscue
M.Tech, Indian Institute of Technology, Kanpur 2001‐ 2003
B. Tech, S G S I T S Indore – 1997‐2001
शिक्षण क्षेत्र
EE698L (Compact Modeling)
EE614 (Solid State Devices - I)
EE370 tutorial (Digital Electronics and Microprocessor Technology)
EE210 tutorial (Microelectronics - I)
ESC201A tutorial and lab (Introduction to Electronics)
EE698F (RF Microelectronics)
व्यावसायिक जुड़ाव
Editor of Institution of Electronics and Telecommunication Engineers (IETE) Technical Review
Senior Member of IEEE
Fellow of INAE
चयनित प्रकाशन
T. Soliman, S. Chatterjee, N. Laleni, F. Muller, T. Kirchner, N. Wehn, T. Kampfe, Y. S. Chauhan, and H. Amrouch, "First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET", Nature Communications, 14, Art. No. 6348, October 2023.
S. S. Parihar, V. M. Santen, S. Thomann, G. Pahwa, Y. S. Chauhan, and H. Amrouch, "Cryogenic CMOS for Quantum Processing: 5nm FinFET based SRAM Arrays at 10K", IEEE Transactions on Circuits and Systems - I, Vol. 70, Issue 8, pp. 3089-3102, August 2023.
D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, S. Choppalli, A. S. Pratiyush, C. Hu, and Y. S. Chauhan, "Physical Insights and Accurate Modeling of Transconductance in Body-contacted Dynamically Depleted SOI MOSFETs", IEEE Transactions on Electron Devices, Vol. 71, Issue 11, pp. 6506-6513, Nov. 2024.
W. Manzoor, A. K. Dutta, G. Pahwa, N. Manzoor, C. Hu, and Y. S. Chauhan, "Extending Standard BSIM-BULK Model to Cryogenic Temperatures", IEEE Transactions on Electron Devices, Vol. 71, Issue 8, pp. 4510-4516, August 2024.
C. K. Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI – Part I: A Compact Model for Dynamically Depleted SOI MOSFETs", IEEE Transactions on Electron Devices, Vol. 71, Issue 4, pp. 2284-2292, April 2024.
A. Kar, S. S. Parihar, J. Z. Huang, H. Zhang, W. Wang, K. Imura, and Y. S. Chauhan, "Characterization and Modeling of 14nm/16nm FinFET Based LDMOS Transistors", IEEE Transactions on Electron Devices, Vol. 71, Issue 1, pp. 62-69, January 2024.
A. Pampori, M. S. Nazir, R. Dangi, M. L. Chou, G. Y. Lee, and Y. S. Chauhan, "A Large-Signal SPICE Model for a Dual-Gate GaN RF Switch with OFF-state Harmonic Control", IEEE Transactions on Electron Devices, Vol. 71, Issue 1, pp. 84-90, January 2024.
N. Bajpai, Paramita Maity, Manish Shah, Amitava Das, and and Y. S. Chauhan, "An Ultra-Low Noise Figure and Multi-band Re-configurable Low Noise Amplifier", IEEE Transactions on Circuits and Systems - I, Vol. 70, Issue 3, pp. 1006-1016, March 2023.
Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, "BSIM6: Analog and RF Compact Model for Bulk MOSFET," IEEE Transactions on Electron Devices, Vol. 61, Issue 2, Feb. 2014.
पुरस्कार एवं फैलोशिप
Senior Member of IEEE
Fellow of INAE (Indian National Academy of Engineering)
Chair Professor - Shri Jagdeo Narain Gupta & Smt. Murti Devi Gupta Chair (2024)
Humboldt Fellowship (2018)
Swarnajayanti Fellowship in Engineering Sciences for 2017-2018
CNR Rao Faculty Award 2017
P K Kelkar Research Fellowship (2015)
Received IBM Faculty Award (2013)
Awarded Ramanujan Fellowship by Department of Science and Technology (2012)
कीवर्ड
Compact Model, SPICE, BSIM-CMG, BSIM-IMG, BSIM6, HEMT Model
पेशेवर अनुभव
2010-2012 - University of California Berkeley
2010 - Tokyo Institutre of Technology, Tokyo, Japan
2007-2010 - IBM Bangalore
2003-2004 - ST Microelectronics